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preliminary information preliminary information describes products that are not in full production at the time of printing. specifications are based on design goals and limited characterization. they may change without notice. contact fairchild semiconductor for current information. www.fairchildsemi.com features accepts 10-bit digital composite, yc, or 8-bit analog composite. outputs 10-bit digital rgb, d1, or yc b c r locks to studio reference r-bus serial interface compatibility fairchild demo board compatibility applications evaluation of tmc22x5y digital video decoder output for tmc2067p7c adc demo board input for genesis 10-bit line doubler board input for tmc2069p7c dac demo board system breadboarding description the TMC2068P7C demonstration board showcases the tmc22x5y digital video decoder. when used with a 10-bit a/d front-end, the decoder accepts digitized composite or yc and outputs d1, digital rgb, or yc b c r . when used without the 10-bit a/d front-end, the on-board tmc22071a or tmc2072 genlocking video digitizer produces an 8-bit digital cvbs signal which the decoder uses to generate outputs. block diagram 72 pin header 96 1 96 1 analog composite video reference 96 way edge connector (female) digital inputs: 10 bit composite/luma 10 bit chroma digital outputs: a/d clock clamp signal digital outputs: 10 bit g/y 10 bit b/u 10 bit r/v d/a clock sync blank 96 way edge connector (male) rbus interface tmc22071a or tmc2072 decoder input logic fpga eprom d.c. supply tmc22x5y 65-2068p-01 TMC2068P7C demonstration board for the tmc22x5y multistandard digital video decoder rev. 0.9.0
TMC2068P7C product specification 2 preliminary information r-bus interface to tmc22071a sda rd0 ra0 gcsb da[1:0] dcsb clamp other outputs rcsb 2:1 scl reset switch w hs decclk other inputs eprom address generator clamp pulse generator fpga control registers and output logic 65-2068p-02 functional description the TMC2068P7C is designed to demonstrate the perfor- mance of the tmc22x5y digital video decoder. for com- plete descriptions of the tmc22x5y and tmc22071a/ tmc2072, please refer to the fairchild semiconductor data book. the TMC2068P7C is designed to be used in conjunc- tion with other fairchild demo boards, namely the tmc2067p7c adc and tmc2069p7c dac boards. the 96 pin edge connectors plug easily into each other. when used together, the boards demonstrate a high perfor- mance 10-bit digital video decoding system. note : to run the TMC2068P7C using the 10-bit tmc2067p7c input, set e2 to ?sel? and close jp3. to run the TMC2068P7C as a stand-alone, using the 8-bit gen- lock cvbs data, set e2 to ?sel?and open jp3. tmc22x5y digital video decoder the TMC2068P7C decoder demonstration board was designed to showcase the tmc22x5y. the tmc22x5y accepts digitized video input on two 10-bit buses, ?over[9:0]?and ?over[9:0]? based on the status of its control registers, it then outputs the data to the output edge connector of the board in a variety of formats. please see table 1 for a listing of video standards and output formats that are loadable to the control registers. the ?pga?section of this documentation contains detailed instructions on how to program the tmc22x5y. after the tmc22x5y control registers have been initially loaded by the fpga and eprom, subsequent changes to the control registers may be made through the r-bus interface and raydemo software. it is important that the control registers be loaded correctly in order to obtain the desired output. once the control registers have been set to output the correct data from the tmc22x5y, then several board switches must also be correctly con?- ured. a bank of switches labeled jp6 allows the user to select between digital rgb and d1 as outputs from the board to the output edge connector. please see table 3. tmc22071a or tmc2072 genlocking video digitizer the tmc22071a or tmc2072 genlocking video digitizer accepts analog composite data through a bnc on the top edge of the board. a 20mhz clock crystal provides the genlock with an input clock. the tmc22071a or tmc2072 outputs digitized cvbs data, horizontal and vertical syncs, and a 27mhz clock. the clock is used to drive the decoder and fpga. like the tmc22x5y, the genlock part must be programmed at startup. detailed instructions on how to do this are in the ?pga?section of this documentation. if the board is run as a stand-alone (i.e. no front-end supply- ing digital video), the genlock accepts analog composite through the bnc and generates 8-bit digital cvbs data as well as horizontal and vertical syncs and a pixel clock. when a 10-bit front end such as the tmc2067p7c is used to supply digital video to the decoder, the genlock still provides horizontal and vertical syncs and a clock to the decoder and fpga. the genlock receives the incoming analog video through either the bnc labeled j1, or through the input edge connector. the option to use analog compos- ite from the input edge connector is default selected at programming. in cases where this video may be too noisy, a short coaxial cable should be connected between j2 on the tmc2067p7c and j1 on the TMC2068P7C. then the default genlock register maps must be changed to accept input from the bnc instead of the input edge connector. this may be done by selecting the ?in1?option for incoming video through the raydemo software. fpga an altera epf8820atc144-4 fpga executes several essential board functions. the fpga controls initial programming of the genlock and decoder, a clamp pulse for the a/d board, a serial interface for the genlock (unless a tmc2072 is installed), and several other important control signals (please see figure 1). figure 1. fpga block diagram
product specification TMC2068P7C 3 preliminary information the altera 8820 controls the eprom during genlock and decoder register map programming. the fpga generates serial interface clocks and address information. it also pro- vides the eprom with addressing for the concurrent parallel interface data output. to program the decoder and genlock, the ea 2-0 switches must be set to the mode of the incoming analog video (see table 1.). verify that switch w, along the bottom edge of the board, is high (in the up position). after the w and ea 2-0 switches are set correctly, press the reset button (s2) and the parts will program. table 1. TMC2068P7C incoming video standard selection the fpga also generates a clamp pulse which is sent back to the a/d board over the 96 way edge connector. the default clamp pulse goes low exactly 199 pixel clock cycles after the horizontal sync pulse (hs) goes low and stays low for exactly 12 pixel clock cycles. if a tmc22071a is the installed genlock, the fpga provides r-bus control of this part by interfacing r-bus data onto the 22071a parallel port. to perform this function, switch w must be low (in the down position). the raydemo reserved tmc22071a r-bus address is 0000000. the fpga control registers may also be written to using the raydemo software. the raydemo fpga r-bus address is 0000001. several other control signals are inputs to or outputs of the fpga. they are brie? described in table 2. for a more complete description of signals going to or coming from the tmc22x5y and tmc22071a/tmc2072, please refer to the fairchild semiconductor data book. note: at powerup, the fpga will only con?ure itself if the ea 2-0 switches are all set low. if the board was powered up with the switches in a different position, adjust the ea 2-0 switches so that they are all low and press the conf (s4) button. ea 2-0 input format video standard output format 000 (fpga configure) n/a n/a 001 composite ntsc yuv 010 y/c ntsc d1 011 composite pal yuv 100 y/c ntsc yuv 101 composite ntsc d1 110 y/c pal yuv 111 composite pal d1 table 2. fpga input and output signal descriptions signal name input/output origin/destination description blank (dac) output output edge connector signal supplied to output connector. buffer output decoder decoder control register select bit . clamp output input edge connector fpga supplied negative-going clamp pulse for the a/d board triggered by hs (horizontal sync) input. clksel output u43 (multiplexer) selects either genlock generated clocks and syncs or externally generated clocks and syncs from the input edge connector. coe10 output input edge connector when e20 is set to ?sel?and e21 is set to ?fpga? this signal controls enabling of the external ??data. conf input s4 (pushbutton labeled ?onf? triggers fpga configuration sequence when pressed then released. cover[9:0] output decoder decoder 10-bit input data to video_b[9:0] input pins cref output output edge connector signal supplied to output connector. cvbs[7:0] input genlock digitized 8-bit genlock output. d1 output output edge connector signal supplied to output connector. d1enfs output output edge connector signal supplied to output connector. da0 output decoder initial programming parallel interface control signal. da1 output decoder initial programming parallel interface control signal.
TMC2068P7C product specification 4 preliminary information dcsb output decoder initial programming parallel interface control signal decclk input u43 (multiplexer) mux-selected pixel clock (either supplied by genlock or from input edge connector) drst output decoder decoder reset control drw output decoder decoder control signal epen output u37 (eprom) eprom enable control fser output p2 (72 pin header) control signal for framestore board fsoe output p2 (72 pin header) control signal for framestore board gcsb output genlock initial programming parallel interface control signal glsda output genlock genlock control signal grst output genlock genlock reset control href output output edge connector signal supplied to output connector hs input u43 (multiplexer) mux-selected negative-going horizontal sync pulse (either supplied by genlock or from input edge connector) imaster/ slave input input edge connector signal which informs the fpga if the previous board wishes to supply clocks and syncs or not master[1:0] output decoder decoder control select bits ntsc/pal output output edge connector signal supplied to output connector pgm_in input input edge connector negative-going reset pulse specific to this board logically anded with pgm_start and reset pgm_out output output edge connector negative-going reset pulse for the board connected to the output connector pgm_start input s2 (pushbutton labeled ?eset? local signal to reset genlock and decoder control registers logically anded with pgm_in and reset ra0 output genlock r-bus to parallel interface control signal rcsb output genlock r-bus to parallel interface control signal rd0 output genlock r-bus to parallel interface control signal reset input/output input/output edge connectors universal negative-going reset pulse logically anded with pgm_start and pgm_in (disable universality with jp42) rgb output output edge connector signal supplied to output connector sww input s1 (switch bank) r-bus enable bit (low to enable) vref output output edge connector signal supplied to output connector vs input u43 (multiplexer) mux-selected negative-going vertical sync pulse (either supplied by genlock or from input edge connector) xrs[3:0] input input edge connector externally generated trs data table 2. fpga input and output signal descriptions (continued) signal name input/output origin/destination description
product specification TMC2068P7C 5 preliminary information quick setup/veri?ation for composite ntsc input, yuv output 1. con?ure jumpers: if running with 10-bit front-end, jp3 must be closed (connected) if running with 8-bit genlock cvbs, jp3 must be open (not connected) if using r-bus interface, jp1 must be closed (con- nected) 2. con?ure slider-switches (push red slider toward speci?d marking on board) : e3hum rejection ?n e4?xck4 e68?vs e67?hs e26?dv e25?dv e24?pxck e23?pxck e21?on e20?off e2?sel e1?etv jp6[0:9]all set to ?y 3. ensure bnc j1 (vin1) is connected to composite ntsc signal. this may be done by attaching a scope probe to tp7. 4. ensure piano-key switch w is in the ?igh?(up) position. 5. ensure piano-key switches ea 2-0 , y are in the ?ow? (down) position. 6. if using r-bus, ensure r-bus connector plugged-in and switches t, u, v match desired tmc22x5y sa 2-0 serial address. 7. plug in power-supply connector and apply power. leds corresponding to applied voltages should light- up. the epf8820 conf_done pin (attached to h25) should go ?igh?to signify that the fpga is correctly programmed. this may be carefully checked with either a scope probe or a dvm. 8. flip piano-key switch ea0 to the ?igh?(up) position. 9. press and release the reset button (s2). the tmc22071a and tmc22x5y should both be pro- grammed. to verify the tmc22071a is functioning correctly, check for presence of sync pulses, vs (tp67) and hs (tp68). likewise, to verify the tmc22x5y is functioning correctly, check for presence of dhsync (tp5) and dvsync (tp6). 10. to utilize r-bus, switch w must be set ?ow?(down). however, it must be returned to ?igh?(up) for every reset of the board. table 3. TMC2068P7C switch and jumper descriptions switch/jumper designator (location on board) option switch setting e1 (bottom middle of board) manual control of decoder set pin ?etx?to control with switch x, ?etv ?to set to vsync pulse e2 (lower middle column) manual control of y data through jp3 when ?sel?high and jp3 closed, external y enabled (genlock cvbs disabled) when ?sel?high and jp3 open, external y disabled (genlock cvbs enabled) e20 (lower middle column) manual control of c data ?off? to disable, ?sel?to defer control to e21 e21 (lower middle column) select enabling of c data ?on?to enable, ?fpga?to defer control to fpga e23, e24 (lower middle column) clock multiplexer bypass ?pxck?to bypass mux and operate on genlock pxck ?ux?to drive clock from selected mux output (e26) e25 (lower middle column) select regular/inverted ldv genlock pixel clock ?dv?for regular, ?dv ?for inverted e26 (lower middle column) select ldv or vsync as a source for external clock option (e24) ?dv?for genlock pixel clock, ?sync?for external vsync
TMC2068P7C product specification 6 preliminary information e3 (upper middle of board) select hum rejection ?n?for normal operation (if switch is set to ?ff?position, incoming composite signal must have an external dc bias) e4 (middle right column) select regular/inverted output clock ?xck4?for regular, ?xck4 ?for inverted e67 (middle right column) select regular/inverted output hsync ?hs?for regular, ?hs ?for inverted e68 (middle right column) select regular/inverted output vsync ?vs?for regular, ?vs for inverted ea0 (bottom right) sets msb of eprom address up to set high, down to set low ea1 (bottom right) sets 2 nd to msb of eprom address up to set high, down to set low ea2 (bottom right) sets 3 rd to msb of eprom address up to set high, down to set low jp1 (top middle) enable r-bus serial interface closed to enable r-bus, open to disable jp3 (lower middle) enable y input when e2 set to ?sel? jp3 is closed to enable y input, open to disable (closed for 10-bit front end operation, open to use genlock 8-bit digitized data) jp42 (middle right) enable s2 (pushbutton) as universal board reset to reset every component on TMC2068P7C and all other boards connected through input and output connectors closed to enable universal reset open to enable reset to fpga only jp5 (middle right) set d1 input to fpga closed to set low, open to set high jp6 (switch column in lower right) select between digital rgb (e.g. tmc2069p7c) or d1 output (e.g. genesis line doubler) through the output connector all set to ?y?(left) for digital rgb all set to ?v?(right) for d1 q (bottom left) sets genlock sa0 r-bus address if tmc2072 is installed up to set high, down to set low r (bottom left) sets genlock sa1 r-bus address if tmc2072 is installed up to set high, down to set low s (bottom left) sets genlock sa2 r-bus address if tmc2072 is installed up to set high, down to set low t (bottom left) sets decoder sa0 r-bus address up to set high, down to set low u (bottom left) sets decoder sa1 r-bus address up to set high, down to set low v (bottom left) sets decoder sa2 r-bus address up to set high, down to set low w (bottom left) r-bus enable down to enable r-bus, up to disable table 3. TMC2068P7C switch and jumper descriptions (continued) switch/jumper designator (location on board) option switch setting
product specification TMC2068P7C 7 preliminary information x (bottom left) sets ?etx?signal high or low up to set ?etx?high, down to set low. used in conjunction with e1 as a decoder input y (bottom right) factory test bit set low table 3. TMC2068P7C switch and jumper descriptions (continued) switch/jumper designator (location on board) option switch setting power supply requirements the TMC2068P7C power supply connector is on the top edge of the board toward the right side. the TMC2068P7C board alone requires a dc power supply voltage of +5v. the connectors for -5v, +12v, and -12v are also made avail- able as a convenience option to power the tmc2067p7c, TMC2068P7C, and tmc2069p7c through a single connec- tor on the TMC2068P7C. the tmc2067p7c and tmc2069p7c do have separate connectors which may be used instead. the +5v supply provides power and voltage references to the tmc22x5y and tmc22071a/tmc2072, as well as driving ttl logic devices. it is for this reason that a bench power supply with short cable lengths is recommended.
TMC2068P7C product specification 8 preliminary information schematics power power edge connector op_conn rv[0..9] bu[0..9] gy[0..9] dhsync dvsync sda scl reset diceclk href cref valid vref pgm_out rgb d1 ntsc/pal blank(dac) fid_0 framestore connector framestore connector yover[0..9] cover[0..9] decclk hs vs fser scl sda reset fsoe d1enfs ckdrive ckdrive vs hs decclk diceclk adclk clksel gvsync ghsync gpxck ixvsync ixhsync ixpxck ldv genlock genlock grst ghsync gcsb gd0 yover[0..9] ga0 gvsync gpxck cvbs[0..7] oecvbs valid an comp/luma sda scl glsda sa0 sa1 sa2 ldv fpga fpga sda scl mpu[0..7] dcsb da1 da0 gcsb gd0 ga0 clamp cvbs[0..7] decclk sww cover[0..9] blank(dac) ntsc/pal d1 coe10 fsoe rgb imaster/slave xrs[0..3] hs vs clksel pgm_out fser pgm_in glsda buffer master0 master1 yoe10 href cref vref d1enfs reset grst drst decoder decoder hs vs yover[0..9] cover[0..9] gy[0..9] bu[0..9] rv[0..9] dhsync dvsync mpu[0..7] drst dcsb da1 da0 scl sda decclk sww buffer master0 master1 sa0 sa1 sa2 fid_0 yover[0..9] cover[0..9] oecvbs an comp/luma pgm_in imaster/slave ixpxck ixhsync xrs[0..3] vs hs reset ixvsync vcc r1 vcc gy[0..9] mpu[0..7] bu[0..9] rv[0..9] sda reset scl clamp decclk da0 da1 dcsb sww dhsync dvsync diceclk cref valid rgb blank\(dac) ntsc/pal d1 xrs[0..3] imaster/slave coe10 fsoe fsoe hs vs vref pgm_out rgb d1 clksel pgm_out sww cover[0..9] reset fser fser sa0 sa1 sa2 pgm_in glsda yoe10 ntsc/pal blank (dac) href d1enfs d1enfs href cref vref ixpxck ixhsync ixvsync gpxck ghsync gvsync clksel adclk diceclk ldv master1 master1 master0 master0 buffer buffer decclk valid gpxck gcsb grst glsda cvbs[0..7] sa0 gvsync ghsync sa1 gd0 sa2 ga0 ldv scl an comp/luma sda vs scl sda hs scl xrs[0..3] drst sda vs vs reset scl sda pgm_in hs yover[0..9] yover[0..9] ixvsync ixpxck adclk clamp yoe10 coe10 sda scl ip_conn scl +5v sda gnd 4 3 2 1 adclk clamp yoe10 coe10 sda scl imaster/slave cover[0..9] ixhsync an comp/luma hs fid_0 reset grst drst 1 ohm 1/4w carbon fb1 f bead jp1 p1 15-83-0064 jumper r3 10k r2 10k 65-2068p-03 figure 2. tmc22x5y.sch
product specification TMC2068P7C 9 preliminary information schematics (continued) vcc vcc vcc -5v +12v vcc -12v vcc vcc vcc vcc vcc csel coff ysel yfpga con cfpga cover[0..9] yover[0..9] cover1 yover2 cover6 cover9 yover3 cover7 cover8 yover1 yover6 yover7 cover0 yover5 yover4 yover9 yover8 yover0 y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 adclk c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 adclk yoe10 oecvbs ixrs0 ixrs1 ixrs2 ixrs3 adclk vs hs idir imaster/slave y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ixhsync ixvsync reset scl clamp sda an comp/luma pgm_in ie ixpxck clamp adclk reset scl sda idir hs vs cover2 cover3 cover4 cover5 coe10 xrs0 xrs1 xrs2 xrs3 xrs0 xrs1 xrs2 xrs3 ixrs1 ixrs3 ixrs2 ixrs0 pgm_in p3a euro96f 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 p3b euro96f 1 33 2 34 3 35 4 36 5 37 6 38 7 39 8 40 9 41 10 42 11 43 12 44 13 45 14 46 15 47 16 48 17 49 18 50 19 51 20 52 21 53 22 54 23 55 24 56 25 57 26 58 27 59 28 60 29 61 30 62 31 63 32 64 p3c euro96f 1 65 2 66 3 67 4 68 5 69 6 70 7 71 8 72 9 73 10 74 11 75 12 76 13 77 14 78 15 79 16 80 17 81 18 82 19 83 20 84 21 85 22 86 23 87 24 88 25 89 26 90 27 91 28 92 29 93 30 94 31 95 32 96 u9 74act821 d1 2 d2 3 d3 4 d4 5 d5 6 d6 7 d7 8 d8 9 d9 10 d10 11 oc 1 clk 13 q1 23 q2 22 q3 21 q4 20 q5 19 q6 18 q7 17 q8 16 q9 15 q10 14 u10 74act821 d1 2 d2 3 d3 4 d4 5 d5 6 d6 7 d7 8 d8 9 d9 10 d10 11 oc 1 clk 13 q1 23 q2 22 q3 21 q4 20 q5 19 q6 18 q7 17 q8 16 q9 15 q10 14 r18 4.75k jp3 yon e2 select c53 0.1uf c54 0.1uf u20 74act245 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g 19 dir 1 b1 18 b2 17 b3 16 b4 15 b5 14 b6 13 b7 12 b8 11 r78 4.75k e20 select e21 select u8d 74f14 9 8 r135 10k r136 10k r134 10k r133 10k yover[0..9] cover[0..9] yoe10 oecvbs clamp ixhsync\ ixvsync\ ixpxck adclk reset sda imaster/slave hs vs coe10 an comp/luma xrs[0..3] pgm_in scl 65-2068p-04 figure 3. ip_conn.sch
TMC2068P7C product specification 10 preliminary information schematics (continued) vcc vcc vcc vcc vcc vcc vcc c8 not installed if cr10 is installed hum rejection on off gcsb ga0 gd0 grst yover2 yover3 yover0 yover8 yover6 yover7 yover5 yover1 yover9 yover4 sda gd0 ga0 gcsb ghsync gvsync sa0 glsda glsda sa0 sa1 sa2 gpxck gvsync cvbs7 cvbs5 cvbs2 sa1 cvbs5 cvbs6 cvbs0 grst gpxck cvbs0 cvbs1 cvbs1 cvbs2 sa2 cvbs6 cvbs4 agnd ghsync cvbs3 cvbs4 cvbs7 20mclk dgnd cvbs3 gnd yover[0..9] cvbs[0..7] cvbs[0..7] r16 75 e3 select c3 22uf/6.3v + tp7 tp c4 22uf/6.3v + c5 6.8pf l1 inductor u6 74f841 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 c 13 oc 1 q1 23 q2 22 q3 21 q4 20 q5 19 q6 18 q7 17 q8 16 q9 15 q10 14 c12 390pf c8 0.1 f c11 150pf j1 bnc 1 2 cr1 1.235v 2 1 y1 20mhz out 5 r10 4.75k c51 0.1 f r12 75 c43 0.1 f c44 0.1 f c45 0.1 f c46 0.1 f c47 0.1 f c48 0.1 f c42 0.1 f c41 0.1 f c40 0.1 f c52 0.1 f e31 select e30 select e32 select r132 33 r131 33 c59 22uf/6.3v + c60 22uf/6.3v + r11 75 tp16 tp h56 1 h60 1 c9 0.1 f r130 33 c7 0.1 f c6 0.1 f r54 4.75k c10 0.1 f r14 3.3k r13 220 r53 4.75k c2 0.1 f u2 tmc22071akhc(2072khc)_2 vin1 65 vin2 61 vin3 58 d0 9 nc 12 (sa2) 3 cs (scl) 5 ext pxck 94 ldv 40 nc 85 nc 19 nc 20 cvbs0 21 cvbs1 22 cvbs5 28 cvbs7 30 ghsync 32 gvsync 33 valid 34 nc 13 nc 76 vref 70 comp 88 rt 68 rb 57 nc 83 cbyp 75 pfd in 77 nc 10 nc 14 cvbs4 25 nc 66 nc 43 clk in 91 cvbs2 23 pxck 45 clk out 93 nc 99 a0 (sa0) 1 (sa1) 2 reset 7 nc 11 nc 15 int 17 cvbs3 24 cvbs6 29 (burl) 31 nc 71 nc 53 nc 54 nc 56 nc 59 nc 62 (fid2) 37 (fid1) 36 (fid0) 35 nc 78 nc 79 nc 80 dds out 82 nc 84 pxck sel 86 r/ w (sda) 4 tp64 tp tp63 tp tp65 tp tp62 tp grst gcsb gd0 ga0 oecvbs cvbs[0..7] yover[0..9] valid ldv an comp/luma sda scl ghsync gvsync glsda sa0 sa1 sa2 gpxck 2 3 4 5 6 7 8 9 10 11 65-2068p-05 figure 4. genlock.sch
product specification TMC2068P7C 11 preliminary information schematics (continued) vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc genlock serial interface decoder parallel interface connect to fpga parallel = low serial = high mpu[0..7] cvbs[0..7] mpu0 mpu1 mpu2 mpu3 mpu4 mpu5 mpu6 mpu7 sda hs vs reset clamp pgm_start epen ea2 y ea1 ea0 rcsb sww ra0 rd0 addr13 addr12 addr11 addr10 addr9 mpu1 mpu2 mpu3 mpu4 mpu5 mpu6 mpu7 mpu0 buffer master0 master1 rgb d1 d1enfs addr2 addr9 da1 ra0 pgm_start sww da0 gcsb rcsb rd0 decclk cvbs4 cvbs5 ntsc/pal d1 ntsc/pal blank\(dac) scl xrs1 xrs2 xrs3 xrs0 xrs1 xrs2 xrs3 scl sda decclk pgm_out pgm_out imaster/slave imaster/slave reset cover0 cover2 cover3 cover4 cover5 cover6 cover7 cover8 cover9 coe10 fsoe coe10 fsoe hs vs clksel fser fser glsda glsda cover9 cover0 cover5 cover4 cover1 cover[0..9] cover6 cover2 cover1 cover7 cover3 cover8 pgm_in pgm_in buffer master0 master1 href vref cref clksel cref href vref d1enfs drst grst pgm_start grst drst drw epen drw rgb cvbs0 cvbs1 cvbs6 cvbs2 cvbs7 cvbs3 clamp blank\(dac) addr[0..13] addr8 addr6 addr0 addr7 addr2 addr10 addr9 addr[0..13] addr3 addr3 addr10 addr12 addr2 addr1 addr6 addr4 addr8 addr1 addr0 addr11 addr5 addr12 addr4 addr3 addr0 addr5 addr13 addr13 addr11 addr8 addr7 addr7 addr5 addr1 addr6 addr4 xrs0 dcsb h6 1 h10 1 h11 1 h16 1 h19 1 r5 4.75k r20 4.75k h2 1 c25 0.1 f r9 4.75k c1 0.1 f r6 4.75k r7 4.75k r4 4.75k r19 4.75k r8 4.75k s4 conf s3 sw dip-4 1 2 3 4 8 7 6 5 s2 reset h3 1 h4 1 h5 1 c33 0.1uf c34 0.1uf c35 0.1uf c36 0.1uf c38 0.1 f c39 0.1 f c37 h18 1 h21 1 h23 1 h25 1 h13 1 h14 1 u37 am27c010 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 ce 22 oe 24 d0 13 d1 14 d2 15 d3 17 d4 18 d5 19 d6 20 d7 21 a16 2 u4a 74f14 1 2 u4b 74f14 3 4 u4f 74f14 13 12 u4e 74f14 11 10 h86 1 tp12 tp tp13 tp tp14 tp tp15 tp jp42 jumper c119 0.1uf c120 0.1uf c121 0.1uf c122 0.1uf c123 0.1uf c124 0.1 f 0.1 f u3 epf8820a-144-4 1 1 2 2 cs 3 ncs 4 5 5 6 6 9 9 10 10 11 11 rdclk 12 clkusr 13 14 14 15 15 gnd 17 128 tdo 18 19 19 rdynbusy 20 21 21 22 22 23 23 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 8 112 24 24 25 25 26 26 29 29 30 30 27 nrs 31 32 32 nws 33 34 34 35 35 36 36 41 41 nconfig 38 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 55 55 39 56 56 57 57 59 59 61 61 62 62 122 63 63 64 64 65 65 66 66 67 67 68 68 54 58 58 ntrst 71 73 73 74 74 add17 75 nstatus 37 add16 76 add15 77 add14 78 add13 79 82 82 add12 83 84 84 add11 85 tms 86 add10 87 tck 88 add9 89 add8 92 80 142 93 93 add7 94 add6 95 tdi 96 add5 97 98 98 16 141 99 99 add4 102 add3 103 add2 104 add1 105 81 add0 106 107 107 108 108 nsp 110 113 113 msel1 72 114 114 115 115 116 116 117 117 118 118 119 119 120 120 121 121 123 123 124 124 125 125 126 126 127 127 100 129 129 130 130 data7 131 42 42 data6 132 data5 133 28 data4 134 data3 135 136 136 data2 137 data1 138 139 139 101 data0 140 dclk 143 conf_done 144 msel0 109 7 69 70 90 91 111 60 40 mpu[0..7] gcsb ga0 dcsb da1 da0 gd0 decclk hs vs cvbs[0..7] clamp yoe10 sww ntsc/pal rgb d1 blank\(dac) cover[0..9] sda pgm_out imaster/slave fsoe clksel fser glsda pgm_in coe10 buffer master0 master1 xrs[0..3] scl d1enfs href cref vref grst drst reset drw 65-2068p-06 figure 5. fpga.sch
TMC2068P7C product specification 12 preliminary information schematics (continued) vcc vcc setv setx mpu[0..7] rv[0..9] bu[0..9] gy[0..9] yover9 yover3 yover8 yover5 yover4 yover7 yover1 yover2 yover6 yover0 swx sww swv sws swr swu swt swq swt swu swv mpu0 mpu1 mpu2 mpu3 mpu4 mpu5 mpu6 dcsb da1 da0 da1 da0 drst drst sww set mpu7 dcsb set gy0 gy1 gy2 gy3 gy4 gy5 gy6 gy7 gy8 gy9 bu0 bu1 bu2 bu3 bu4 bu5 bu6 bu7 bu8 bu9 rv0 rv1 rv2 rv4 rv5 rv6 rv7 rv8 rv9 rv3 sww yover[0..9] cover3 cover2 cover7 cover[0..9] cover9 cover4 cover6 cover5 cover0 cover1 cover8 buffer master0 master1 swq swr sws buffer master0 master1 swq swr sws h1 1 s1 sw dip-8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 e1 select u1 tmc22153khc buffer 50 master1 88 master0 87 videoa_9 86 videoa_8 85 videoa_7 84 videoa_6 83 videoa_5 82 videoa_4 81 videoa_3 80 videoa_2 79 videoa_1 78 videoa_0 77 videob_9 75 videob_8 74 videob_7 73 videob_6 72 videob_5 71 videob_4 70 videob_3 69 videob_2 68 videob_1 67 videob_0 66 clock 89 ldv 3 hsync 48 vsync 49 a_1 63 a_0 62 d_7 45 d_6 44 d_5 43 d_4 42 d_3 41 d_2 38 d_1 37 d_0 36 cs 60 r/ w 61 set 52 reset 51 ser 53 sa_2 56 sa_1 55 sa_0 54 scl 59 sda 58 g/y_9 93 g/y_8 94 g/y_7 95 g/y_6 96 g/y_5 97 g/y_4 98 g/y_3 99 g/y_2 100 g/y_1 1 g/y_0 2 b/cb_9 6 b/cb_8 7 b/cb_7 8 b/cb_6 9 b/cb_5 10 b/cb_4 11 b/cb_3 12 b/cb_2 13 b/cb_1 14 b/cb_0 15 r/cr_9 18 r/cr_8 19 r/cr_7 20 r/cr_6 21 r/cr_5 22 r/cr_4 23 r/cr_3 24 r/cr_2 25 r/cr_1 26 r/cr_0 27 fid_2 33 fid_1 32 fid_0 31 avout 30 dhsync 34 dvsync 35 tp1 tp tp2 tp tp3 tp tp4 tp tp5 tp tp6 tp rn1 4.7k 1 3 4 5 6 7 8 9 10 2 c26 0.1uf c27 0.1uf c28 0.1uf c29 0.1uf c30 0.1uf c31 0.1uf c32 0.1uf cover[0..9] yover[0..9] decclk hs vs scl mpu[0..7] dcsb da1 da0 drst gy[0..9] bu[0..9] rv[0..9] dhsync dvsync sww buffer master0 master1 sa0 sa1 sa2 sda fid_0 drw 65-2068p-07 figure 6. decoder.sch
product specification TMC2068P7C 13 preliminary information schematics (continued) vcc vcc place components on this page close to the genlock. ldv ldv gpxck gpxck mux mux ldv vsync adclk diceclk decclk u43 sn74f157a 1a 2 1b 3 2a 5 2b 6 3a 11 3b 10 4a 14 4b 13 g 15 a/b 1 1y 4 2y 7 3y 9 4y 12 tp68 tp tp67 tp tp66 tp u77a 74f240 a1 2 a2 4 a3 6 a4 8 g 1 y1 18 y2 16 y3 14 y4 12 e24 select e23 select u8f 74f14 13 12 u77b 74f240 a1 11 a2 13 a3 15 a4 17 g 19 y1 9 y2 7 y3 5 y4 3 u8c 74f14 5 6 e25 select e26 select c117 0.1 f c118 0.1 f adclk decclk diceclk ghsync ixhsync gvsync ixvsync ixpxck clksel gpxck hs vs ldv figure 7. ckdrive.sch
TMC2068P7C product specification 14 preliminary information schematics (continued) vcc 10 bit framestore for decoder comb filter cover3 cover2 yover0 yover1 yover2 yover3 yover6 yover7 yover8 yover9 yover4 yover5 cover4 cover5 cover6 cover7 cover8 cover9 cover1 cover0 p2 simm72 2 3 4 5 6 7 8 9 gnd gnd gnd gnd 1 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 19 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 2 3 4 5 6 7 8 9 vdd 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 vdd 31 32 33 34 35 36 37 38 40 41 42 43 44 45 46 47 vdd 49 50 51 52 53 54 55 56 57 58 vdd 60 61 62 63 64 65 66 67 68 69 70 71 72 hs vs yover[0..9] cover[0..9] scl sda decclk reset fsoe vs hs decclk fser d1enfs figure 8. framestore connector
product specification TMC2068P7C 15 preliminary information schematics (continued) vdd vdda +12v -12v vcc +5v -5v ground test points unused gates p12v gnd p5v n12v gnd n5v c16 0.01 f 50v c13 22 f 35v + c15 0.1 f 50v c14 0.47 f 35v + fb4 f bead fb5 f bead c20 0.01uf 50v c17 22uf 35v + c21 22uf 35v + c23 0.1uf 50v c19 0.1uf 50v c18 0.47uf 35v + c22 0.47uf 35v + c24 0.01uf 50v tp10 +12v tp8 +5v tp11 -12v cr3 1n4004 cr6 1n4004 cr7 1n4004 cr2 red led cr4 red led cr10 orange led cr9 orange led tp9 -5v c113 22 f 35v + fb3 f bead c115 0.1 f 50v c114 0.47 f 35v + c116 0.01 f 50v cr8 1n4004 tp90 loop tp91 loop tp92 loop tp93 loop tp94 loop u4c 74f14 5 6 jp4 power6 1 2 3 4 5 6 u4d 74f14 9 8 figure 9. power.sch
TMC2068P7C product specification 16 preliminary information schematics (continued) +12v vcc vcc -5v -12v vcc 96 way edge connections from the decoder board may need to remove these rv[0..9] bu[0..9] rv[0..9] gy[0..9] gy[0..9] y[0..9] y[0..9] rv2 rv3 rv4 rv5 rv6 rv7 rv8 rv1 rv0 dhsync dvsync rv9 bu4 bu7 bu6 bu0 bu9 bu1 bu3 bu5 bu8 bu2 sda scl reset odd in href cref lock pxck4 rv2 rv3 rv4 rv5 rv6 rv7 rv8 rv1 rv0 rv9 gy2 gy3 gy4 gy7 gy9 gy5 gy8 gy0 gy6 gy1 y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 gy2 gy3 gy4 gy5 pgm_out pxck4 cref dvsync dhsync vref odd in ntsc/pal rgb lock d1 reset scl sda blank\(dac) href vref rgb dhsync dvsync d1 pgm_out blank\(dac) ntsc/pal e4 select r21 4.75k jp5 d1en jp6a hdr10x3 1 4 7 10 13 16 19 22 25 28 jp6b hdr10x3 2 5 8 11 14 17 20 23 26 29 jp6c hdr10x3 3 6 9 12 15 18 21 24 27 30 p4a euro96m 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 p4b euro96m 1 33 2 34 3 35 4 36 5 37 6 38 7 39 8 40 9 41 10 42 11 43 12 44 13 45 14 46 15 47 16 48 17 49 18 50 19 51 20 52 21 53 22 54 23 55 24 56 25 57 26 58 27 59 28 60 29 61 30 62 31 63 32 64 p4c euro96m 1 65 2 66 3 67 4 68 5 69 6 70 7 71 8 72 9 73 10 74 11 75 12 76 13 77 14 78 15 79 16 80 17 81 18 82 19 83 20 84 21 85 22 86 23 87 24 88 25 89 26 90 27 91 28 92 29 93 30 94 31 95 32 96 e67 select e68 select u8e 74f14 11 10 u8a 74f14 1 2 u8b 74f14 3 4 r137 10k dhsync dvsync gy[0..9] bu[0..9] rv[0..9] sda scl reset fid_0 href cref valid diceclk vref rgb d1 pgm_out blank\(dac) ntsc/pal figure 10. op_conn.sch
product specification TMC2068P7C 17 preliminary information input 96 way connector (female) description and notes row a row b row c 32 +5v 32 gnd 32 +5v 31 d1 or r/v [bit 0] 31 +5v 31 gnd 30 d1 or r/v [bit 1] 30 +5v 30 pxck 29 d1 or r/v [bit 2] 29 +5v 29 gnd 28 d1 or r/v [bit 3] 28 gnd 28 pck 27 d1 or r/v [bit 4] 27 analog composite/luma 27 gnd 26 d1 or r/v [bit 5] 26 gnd 26 cref 25 d1 or r/v [bit 6] 25 analog chroma 25 gnd 24 d1 or r/v [bit 7] 24 xen 24 vsync 23 d1 or r/v [bit 8] 23 gnd 23 hsync 22 d1 or r/v [bit 9] 22 xdir 22 href 21 comp, g/y, or luma [bit 0] 21 xhsync 21 vref 20 comp, g/y, or luma [bit 1] 20 xvsync 20 odd in 19 comp, g/y, or luma [bit 2] 19 xpxck 19 gnd 18 comp, g/y, or luma [bit 3] 18 xrs [bit 3] 18 ntsc/pal 17 comp, g/y, or luma [bit 4] 17 xrs [bit 2] 17 clamp pulse 16 comp, g/y, or luma [bit 5] 16 xrs [bit 1] 16 rgb 15 comp, g/y, or luma [bit 6] 15 xrs [bit 0] 15 14 comp, g/y, or luma [bit 7] 14 gnd 14 13 comp, g/y, or luma [bit 8] 13 -5v 13 12 comp, g/y, or luma [bit 9] 12 -5v 12 lock 11 chroma or b/u [bit 0] 11 -5v 11 d1 10 chroma or b/u [bit 1] 10 gnd 10 reset 9 chroma or b/u [bit 2] 9 pgm_in 9 scl 8 chroma or b/u [bit 3] 8 -12v 8 gnd 7 chroma or b/u [bit 4] 7 -12v 7 sda 6 chroma or b/u [bit 5] 6 ie (input enable) 6 oe (output enable) 5 chroma or b/u [bit 6] 5 gnd 5 blank (dac) 4 chroma or b/u [bit 7] 4 4 3 chroma or b/u [bit 8] 3 3 2 chroma or b/u [bit 9] 2 +12v 2 +12v 1 gnd 1 gnd 1 gnd
TMC2068P7C product specification 18 preliminary information input edge connector design notes figure 11. y/composite lpf and clamp circuit tmc2242 signal flow forward signal flow backward tmc2072 tmc3003 eprom high quality lpf low quality lpf low quality lpf low quality lpf +5v to -5v 2:1 mux high quality lpf high quality lpf fpga d.c. supply sw1 tmc22153 decoder input logic 10 bit adcs digital lpfs sw1 sw2 1 32 1 32 1 32 1 32 tmc1185 tmc1185 tmc2242 chrominance bpf and clamp circuit boards with different revision letters may not be compatible; damage may occur if they are connected together. xpxck is a two times pixel clock fed backward xhsync and xvsync are timing reference signals fed backward the master/slave signal states if a board is a master or a slave board. this signal is fed forward. a master board produces the pxck, hsync, and vsync signals, and a slave board expects to receive xpxck, xhsync, xvsync, etc . xdir is fed forward and controls in which direction the xrs[3:0] data ?ws. pgm_in is a negative going pulse, logically anded with the onboard program start pulse, for initiating the programming sequence for components on that board. care must be taken to ensure that multiple devices do not try to drive the rbus at any given time. minimum width of pgm_in is 1us. the reset pin on the input edge connector should be connected directly to the reset pin on the output connector. a link should be used to connect any pulse to the reset line. the master/slave, xdir, pgm_in and reset pins on the input edge connector should be connected to +5v through a 10k pull up resistor. the clamp signal is fed backward from a master to a slave board. the clamp signal should not be fed forward.
product specification TMC2068P7C 19 preliminary information output 96 way connector (male) description and notes row a row b row c 1 +5v 1 gnd 1 +5v 2 d1 or r/v [bit 0] 2 +5v 2 gnd 3 d1 or r/v [bit 1] 3 +5v 3 pxck 4 d1 or r/v [bit 2] 4 +5v 4 gnd 5 d1 or r/v [bit 3] 5 gnd 5 pck 6 d1 or r/v [bit 4] 6 analog composite/luma 6 gnd 7 d1 or r/v [bit 5] 7 gnd 7 cref 8 d1 or r/v [bit 6] 8 analog chroma 8 gnd 9 d1 or r/v [bit 7] 9 xen 9 vsync 10 d1 or r/v [bit 8] 10 gnd 10 hsync 11 d1 or r/v [bit 9] 11 xdir 11 href 12 comp, g/y, or luma [bit 0] 12 xhsync 12 vref 13 comp, g/y, or luma [bit 1] 13 xvsync 13 odd in 14 comp, g/y, or luma [bit 2] 14 xpxck 14 gnd 15 comp, g/y, or luma [bit 3] 15 xrs [bit 3] 15 ntsc/pal 16 comp, g/y, or luma [bit 4] 16 xrs [bit 2] 16 clamp pulse 17 comp, g/y, or luma [bit 5] 17 xrs [bit 1] 17 rgb 18 comp, g/y, or luma [bit 6] 18 xrs [bit 0] 18 19 comp, g/y, or luma [bit 7] 19 gnd 19 20 comp, g/y, or luma [bit 8] 20 -5v 20 21 comp, g/y, or luma [bit 9] 21 -5v 21 lock 22 chroma or b/u [bit 0] 22 -5v 22 d1 23 chroma or b/u [bit 1] 23 gnd 23 reset 24 chroma or b/u [bit 2] 24 pgm_out 24 scl 25 chroma or b/u [bit 3] 25 -12v 25 gnd 26 chroma or b/u [bit 4] 26 -12v 26 sda 27 chroma or b/u [bit 5] 27 ie (input enable) 27 oe (output enable) 28 chroma or b/u [bit 6] 28 gnd 28 blank (dac) 29 chroma or b/u [bit 7] 29 29 30 chroma or b/u [bit 8] 30 30 31 chroma or b/u [bit 9] 31 +12v 31 +12v 32 gnd 32 gnd 32 gnd
TMC2068P7C product specification 20 preliminary information output edge connector design notes figure 12. y/composite lpf and clamp circuit tmc2242 signal flow forward signal flow backward tmc2072 tmc3003 eprom high quality lpf low quality lpf low quality lpf low quality lpf +5v to -5v 2:1 mux high quality lpf high quality lpf fpga d.c. supply sw1 tmc22153 decoder input logic 10 bit adcs digital lpfs sw1 sw2 1 32 1 32 1 32 1 32 tmc1185 tmc1185 tmc2242 chrominance bpf and clamp circuit boards with different revision letters may not be compatible; damage may occur if they are connected together. xpxck is a two times pixel clock fed backward xhsync and xvsync are timing reference signals fed backward the master/slave signal states if a board is a master or a slave board. this signal is fed forward. a master board produces the pxck, hsync, and vsync signals, and a slave board expects to receive xpxck, xhsync, xvsync, etc . xdir is fed forward and controls in which direction the xrs[3:0] data ?ws. pgm_out negative going signal pulse for initiating programming of down stream boards, generated once the devices on the board have been programmed. care must be taken to ensure that multiple devices do not try to drive the rbus at any given time. the minimum width of pgm_out is 1 m s. the reset pin on the output edge connector should be connected directly to the reset pin on the input connector. a link should be used to connect any pulse to the reset line. the master/slave, xdir, pgm_out and reset pins on the output edge connector should be connected to +5v through a 10k pull up resistor. the clamp signal is fed backward from a master to a slave board. the clamp signal should not be fed forward.
product specification TMC2068P7C 21 preliminary information table 4. TMC2068P7C parts list item qty. part name reference designator description 1 1 linear technology lt1004ch- 1.235 cr1 1.235v 2 1 hewlett packard: hlmp-1600 cr2, red 3 1 hewlett packard: hlmp-1601 cr4 red 4 4 minireel: 76-4004 cr3,cr6,cr7, cr8 1n4004 5 1 hewlett packard: hlmp-1620 cr9 orange 6 1 hewlett packard: hlmp-1621 cr10 orange 7 46 minireel: 605-611 c1,c2,c6,c7,c8,c9,c10 c15,c19,c23,c25,c26 c27,c28,c29,c30,c31 c32,c33,c34,c35,c36 c37,c38,c39,c40,c41 c42,c43,c44,c45,c46 c47,c48,c51,c52,c53 c54,c115,c117,c118 c119,c120,c121,c122 c123 0.1uf 8 4 minireel: 643-822 c3,c4,c59,c60 22 uf/10v 9 1 minireel: 605-168 c5 6.8pf 10 1 minireel: 605-315 c11 150pf 11 1 minireel: 605-339 c12 390pf 12 4 minireel: 645-823 c13,c17,c21,c113 22uf/ 25v 13 4 minireel: 641-647 c14,c18,c22.c114 0.47uf/ 25v 14 4 minireel: 605-510 c16,c20,c24,c116 0.01uf 15 15 secma: 090320102 e1,e2,e3,e4,e20,e21,e23e24,e 25,e26,e30,e31,e32e67,e68 select 16 5 fair-rite: 2743019447 fb1,fb2,fb3,fb4,fb5 f bead 17 19 h1,h2,h3,h4,h5,h6,h10 h11,h13,h14,h16,h18 h19,h21,h23,h25,h56 h60,h86 pth 18 2 amp: 103747-2 jp1,jp42 jumper 19 1 amp: 103747-2 jp3 yon 20 1 beau: 870503 beau: 871803 jp4 power6, terminal block and socket 21 1 amp: 103747-2 jp5 d1en 22 1 amp: 103817-8 jp6 hdr10x3 23 1 amphenol: 31-5431 j1 bnc 24 1 minireel: 667-210 l1 10 uh 1210 25 1 molex: 15-83-0064 p1 r-bus 26 1 amp: 4-103186-0 p2 hdr40x2 (simm72) 27 1 amp: 650461-4 p3 euro96f 28 1 amp: 650473-5 p4 euro96m 29 1 dale: csc10a-01-472 rn1 4.7k 30 1 rohm: r25xt-68j1r0 r1 1 ohm 1/4w carbon
TMC2068P7C product specification 22 preliminary information related products tmc2067p7c decoder demonstration board tmc2069p7c adc demonstration board tmc2070p7c r-bus interface board raydemo software 31 6 minireel: 615-510 r2,r3,r133,r134,r136 r137 10k 32 14 minireel: 615-447 r4,r5,r6,r7,r8,r9,r10 r18,r19,r20,r21,r53 r54,r78 4.75k 33 3 minireel: 615-275 r11,r12,r16 75 34 1 minireel: 615-822 r13 220 35 1 minireel: 615-844 r14 3.3k 36 3 minireel: 615-808 r130,r131,r132 33 37 1 alcoswitch: adp-8 s1 sw dip-8 38 1 itt canon:ksc221jb s2, s4 reset, con 39 1 alcoswitch: adp-4 s3 sw dip-4 40 19 mouser: me151-203-100 tp1,tp2,tp3,tp4,tp5 tp6,tp7,tp12,tp13,tp14tp15, tp16,tp62,tp63 tp64,tp65,tp66,tp67 tp68 tp 41 1 mouser: me151-203-100 tp8 +5v 42 mouser: me151-203-100 tp9 -5v 43 1 mouser: me151-203-100 tp10 +12v 44 1 mouser: me151-203-100 tp11 -12v 45 5 tp90,tp91,tp92,tp93 tp94 loop 46 1 fairchild: tmc22153khc u1 tmc22153khc 47 1 fairchild: tmc22071akhc u2 tmc22071akhc (2072khc)_2 48 1 altera: epf8820a-144-4 u3 fpga, epf8820a-144-4 49 2 motorola: mc74f14d u4,u8 74f14 50 1 phillips: 74f841d u6 74f841 51 2 phillips: 74f821d u9,u10 sn74act821 52 1 amp: 544223-3 u37 eprom socket, 32 pin 53 1 motorola: mc74f157ad u43 74f157a 54 1 motorola: mc74f240dw u77 74f240 55 1 abrocon: ach-20.000mhz-c y1 20mhz item qty. part name reference designator description
product specification TMC2068P7C 23 preliminary information notes:
TMC2068P7C product specification pr eliminar y infor mation 5/20/98 0.0m 001 stock# ds7002068p 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1 . life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2 . a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com o r dering in f ormation th e tmc2070p7c parallel port to r- b us board, interface cable, raydemo software, and all rel e v ant documentation are included in th e TMC2068P7C purchase price. th e tmc2067p7c , TMC2068P7C , tmc2069p7c , tmc2070p7c, cable, software and documentation are a v ailable in the tmc2068 kit. a schematic database is a v ailable in orcad ? format, along with ep r om maps. more information on the fpga design is also a v ailable. contact the factor y . th e TMC2068P7C demonstration board, design documentation, and software are pr o vided as a design e xample for the cus- tomers of f airchild. f airchild makes no warranties, e xpress, statutor y , or implied r e garding merchantability or ?ness for a particular purpose. fcc compliance this board is intended for the e v aluation of f airchild products onl y . this d e vice has not been appr o v ed by the federal communications commission (fcc) . this d e vice is not and may not be o f fered for sale or lease or sold or leased until the appr o v al of the fcc has been obtained. p r oduct number t emperature range speed grade screening p a c k age p a c kage marking TMC2068P7C 25 c 27 mhz commercial 4" b y 5" p r inted circuit board TMC2068P7C

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